Since the invention of integrated circuits, the semiconductor industry has experienced continuous rapid growth due to constant improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in the minimum feature size, allowing more components to be integrated into a given chip area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvements in 2D integrated circuit formation, there are physical limitations to the density that can be achieved in two dimensions. One of these limitations is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
An additional limitation comes from the significant increase in the number and length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit RC delay and power consumption increase.
Efforts for resolving the above-discussed limitations commonly include the use of three-dimensional integrated circuits (3DICs) and stacked dies. Through-silicon vias (TSVs) are often used in 3DICs and stacked dies for connecting dies. In this case, TSVs are used to connect the integrated circuits on a die to the backside of the die. In addition, TSVs are also used to provide a short grounding path to connect the ground in the integrated circuits to the backside of the die, which is typically covered by a grounded aluminum film.
Typically, the formation of TSVs includes forming TSV openings, forming TSV liners in the TSV openings, and filling metallic materials into the remaining portion of the TSV openings. TSV openings often have high aspect ratios, for example, greater than about 7. It is thus difficult to form conformal TSV liners. FIGS. 1A through 1G illustrate a conventional process for forming TSV liners, which process comprises multiple etch and re-deposition cycles. Referring to FIG. 1A, TSV opening 102 is formed in substrate 100. In FIG. 1B, TSV liner 104 is deposited on sidewalls of TSV opening 102 using chemical vapor deposition (CVD). It is noted that portions of TSV liner 104 close to the top portion of TSV opening 102 are very thick, while portions of TSV liner 104 close to the bottom portion of TSV opening 102 are very thin, or do not exist at all. With such a profile of TSV liner 104, it is difficult to fill a metallic material into TSV opening 102. Therefore, as shown in FIG. 1C, an etch-back is performed to reduce the thickness of TSV liner 104, particularly the top portion of TSV liner 104. A second deposition is then performed, as shown in FIG. 1D. FIGS. 1E, 1F and 1G illustrate the repeated etch-back and deposition of TSV liner 104. The above-discussed process has the effect of increasing the conformity of TSV liner 104. However, even with the repeated etch-back and re-deposition cycles, the sidewall coverage of TSV liner 104 is still unsatisfactory. Particularly, the bottom portions of TSV liner 104 are often much thinner than the top portions, especially in TSV openings having very high aspect ratios.
In the above-discussed cycles, sub-atmospheric chemical vapor deposition (SACVD) may also be used to deposit TSV liner 104. The profile of the resulting liner is better than when it is formed using CVD. However, the cost of SACVD is high. In addition, the SACVD can only be used to deposit SiO2, which has a k value of 3.9. It cannot be used to form low-k dielectric layers.
Accordingly, new TSV formation processes are needed to form TSV liners having better coverage without incurring additional manufacturing cost.